1. Technical Field
The present invention relates in general to logic circuits and, in particular, to dynamic logic circuits. More particularly, the present invention relates to a fully dynamic logic network that utilizes a dynamic logic circuit, such as a dynamic NAND or a dynamic NOR gate, in conjunction with dynamic switching circuits such as dynamic domino logic gates.
2. Description of the Related Art
Integrated complementary metal-oxide-semiconductor (CMOS) logic circuits typically come in two types; static and dynamic field effect transistor (FET) logic gates. A static logic gate generally does not require an external clock signal to control its operation. Furthermore, the static logic gate can maintain its state for as long as a supply voltage is applied to it. A dynamic logic gate, on the other hand, generally does not hold its state indefinitely and requires an external clock signal to operate the circuit, e.g., in a precharge and evaluation mode. Dynamic CMOS logic gates, in contrast to static gates, generally tend to yield better performance, consume less power and typically require less silicon area for fabrication.
Dynamic switching circuits are designed to operate in two phases, a precharged phase and an evaluate phase. During the precharge phase, nodes within the dynamic circuit are set to predefined voltage levels. During the evaluate phase, the dynamic circuit nodes switch from their precharge state depending on the logic function of the dynamic switching circuit. Dynamic switching circuits are often cascaded together such that the output of one dynamic circuit becomes the input to the logic function of a second dynamic circuit. Each dynamic circuit is precharged in parallel, i.e., at the same time. However, each dynamic circuit evaluates in series. Dynamic circuits cascaded in this fashion are sometimes referred to as domino circuits in that the precharge sets up each dynamic circuit and a first dynamic circuit evaluation sets off a series of evaluations in each succeeding dynamic circuit until a final output is received.
A conventional dynamic domino circuit typically comprises a logic evaluation, or combinational logic, circuit that implements the desired logic function followed by a negative logic gate. A negative logic gate is necessary because the domino CMOS gates are generally non-inverting and generally do not provide a universal set of logic elements. However, they are compatible with CMOS static gates. Consequently, most logic functions can be implemented with domino CMOS alone or in combination with static negative logic gates which may be either a NOR, NAND or INVERTER gate. Since the performance of any given digital circuit design generally depends on the number of logic states in the critical paths and the delays at each stage, the utilization of the static NAND or static NOR gates are preferred over the static INVERTER in many applications. Static NAND and NOR gates allow for so-called complex-domino gates, in which the outputs of two or more dynamic structures are logically combined in the static gate. This allows for larger, more complex logic functions than the standard domino circuits would otherwise allow for. Additionally, the static NAND and NOR gates also provide an opportunity to split wide dynamic xe2x80x9ctrees,xe2x80x9d thus improving noise margins. However, when utilized to drive xe2x80x9cheavyxe2x80x9d loads, the static NAND and NOR gates typically suffer performance degradation faster than static inverter gates.
Accordingly, what is needed in the art is an improved switching logic network topology that mitigates the limitations discussed above. More particularly, what is needed in the art is a fully dynamic switching network that allows the utilization of NAND and NOR gates without incurring the penalty of faster performance degradation under heavy load conditions.
To address the above-discussed deficiencies of the prior art, the present invention provides a fully dynamic logic network. In one embodiment, the dynamic logic network includes a number of dynamic switching circuits, where each of dynamic switching circuits generates an output signal. In an advantageous embodiment, each of the dynamic switching circuits is a dynamic domino gate. The dynamic logic network also includes a dynamic logic circuit that is coupled to the dynamic switching circuits. The dynamic logic circuit, in turn, includes a clock generation circuit and a logic switching circuit that in a preferred embodiment is a dynamic NOR, or alternatively, a NAND gate. The clock generation circuit receives the output signals from the dynamic switching circuits and generates, in response thereto, a control signal. The logic switching circuit also receives the output signals from the dynamic switching circuits and generates a logic output signal in response to a state of the control signal generated by the clock generation circuit.
The present invention discloses a novel fully dynamic logic switching network that utilizes a dynamic logic gate, such as a dynamic NAND or NOR gate, in place of the static gates presently employed in conventional circuits. The driveability problem inherent in static NAND and NOR logic gates are substantially obviated allowing the utilization of NAND and NOR logic gates in dynamic circuits that are driving heavy loads. Furthermore, since the output stage of the dynamic logic switching network of the present invention are dynamic in nature, its performance is superior to the conventional dynamic circuits utilizing static logic gates at their output stage. This is due to the reduced capacitance seen on the precharge nodes of the dynamic switching circuits resulting from the smaller device sizes required for the transistors in the dynamic logic gate as opposed to transistors required for a static logic gate.
The foregoing description has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest